The scourge of x86 emulation
Points and comments are a snapshot, not live.
Emulating x86's strict memory model on ARM causes severe performance penalties without hardware TSO support.
FEX, an x86-to-ARM translation framework, explains that emulating x86 Total Store Ordering (TSO) on ARM's weak memory model forces use of costly load-acquire/store-release instructions, degrading performance up to 85% on some CPUs (e.g., AmpereOne). ARMv8.3's FEAT_LRCPC extension improves this by adding RCpc load instructions, but unaligned accesses trigger alignment faults, requiring fallback to memory barriers (DMB) that halve throughput. Apple's M1 chips solve this with a thread-wide TSO toggle, allowing regular loads/stores. The article concludes that a hardware TSO mode is the best path for high-performance x86 emulation.
What commenters are saying
Commenters note FEX is used in Valve's Steam Frame and Crossover Beta. A debate arises over why Valve doesn't mandate a bytecode format for games. Multiple replies argue existing game backlogs, IP limbo, and developer resistance make emulation the only practical path. One commenter highlights that Apple's M1 chips solved TSO emulation with a hardware mode, calling it another way Apple leads the industry.