Solving the Jane Street reverse engineering challenge
Points and comments are a snapshot, not live.
An engineer reverse-engineers an ASIC from a GDS file using custom Python code.
The author recounts solving Jane Street's ASIC reverse-engineering challenge. They read a GDSII file (a chip layout format) containing ~10k cells from the sky130 process design kit. Building from scratch with gdstk and shapely, they extracted a logic netlist by detecting overlapping geometry on adjacent layers, converted it to Verilog, and ran simulations. The warmup puzzle contained shift registers, an adder, and a comparitor. The real puzzle had 81 cell types and 120-bit input. They traced the output back through shift registers using a recurrence-relation method with a constraint solver (a spreadsheet generating Verilog) to narrow the input state. The author submitted a confirmed bug report about a floating wire.
What commenters are saying
Commenters praised the author's perseverance but noted they made the problem harder than necessary. Several pointed to existing EDA tools: librelane for the open silicon tool suite, magic for circuit extraction from GDS, and SymbiYosys or Z3 for formal verification. One commenter described using Z3 to convert the netlist into equations and solve for the correct input directly. Another mentioned using an LLM (ChatGPT 5.6) to solve the challenge in an hour. Two camps emerged around authenticity: some valued the learn-by-doing approach, while others noted the availability of more efficient tooling. A discussion arose about whether Jane Street genuinely values highly autonomous engineers or merely seeks above-average ticket pushers.