PlayStation Architecture
Deep technical breakdown of PlayStation CPU architecture, from MIPS R3000A selection through coprocessor integration and pipeline hazards.
The PlayStation CPU is a system-on-chip (Sony CXD8530BQ) built by LSI Logic around a MIPS R3000A-compatible core running at 33.87 MHz. Sony selected the cost-effective R3000A over SGI's flagship R4000 to balance performance with console affordability. The chip includes 32 general-purpose registers, a 5-stage pipeline, 4 KB instruction cache, and 1 KB of Scratchpad RAM (no data cache). Sony paired this with three coprocessors: System Control Coprocessor (CP0) for cache and interrupts, Geometry Transformation Engine (CP2) for 3D math, and Motion Decoder (MDEC) for JPEG-like decompression at 9,000 macroblocks per second. A DMA controller handles independent memory transfers for graphics, audio, and CD I/O. The omission of a floating-point unit meant developers relied on fixed-point arithmetic. MIPS I's susceptibility to pipeline hazards required developers to manually insert delay slots after branch and jump instructions.
What HN community is saying
Commenters praised Copetti's technical depth and clarity, with comparisons to similar deep-dives by Fabien Sanglard. A note that this article was originally published in 2019 with updates since. Discussion shifted to PS1 graphics aging: CRT display advocates argue PS1 games hold up well on original hardware or with CRT shaders, while some noted the console's characteristic vertex wobble and lack of perspective-corrected texture mapping. One commenter shared porting experience with Metal Gear Solid, describing how Konami engineers used memory region aliasing to pack data into pointer bits. Consensus that PS1's 2 MB RAM and 1 MB VRAM constraints produced an impressive library of games, with a smaller point about PS2's significantly larger jump in capability enabling games like GTA 3 only through aggressive streaming and memory fragmentation tricks.