IBM debuts sub-1 nanometer chip technology
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IBM announces the world's first sub-1 nanometer chip with a 3D nanostack architecture.
IBM unveiled a sub-1 nm chip technology at the 0.7 nm (7 angstrom) node, featuring a three-dimensional "nanostack" architecture that vertically stacks transistors. The chip packs nearly 100 billion transistors on a fingernail-sized die, nearly double the density of IBM's 2 nm chip from 2021. IBM projects 50% more performance or 70% greater energy efficiency vs. its 2 nm node. The design was experimentally validated with CMOS integration and functional inverter operation. IBM sees a path to production in as early as five years.
What commenters are saying
Commenters questioned how IBM commercializes these breakthroughs, noting the company no longer owns production fabs. Several explained IBM's model: licensing technology and providing process support to fabs like Rapidus (which licensed 2 nm) and others. A detailed reply clarified IBM's role in the semiconductor ecosystem, using the colorful metaphor of a "writhing mass of copulating tapeworms." Others debated the marketing of node names, noting that "0.7 nm" is a performance-equivalent label, not a physical dimension-actual features remain in the ~5 nm range, achieved through 3D stacking.