Assembly Hall of Shame
Points and comments are a snapshot, not live.
A research project finds the single slowest x86 instruction by sabotaging CPU performance.
The Assembly Hall of Shame ranks x86 instructions by worst-case latency, aiming for a performance floor rather than optimization. The current champion is `fxrstor64` on an AMD Ryzen 7 5800H, scoring 198 billion cycles (62 seconds). The strategy loads 512-byte FPU state from high-latency PCIe MMIO while other cores pound a different register with reads, saturating the PCIe root complex. Other notable entries include unaligned `vmovdqu ymm` (4.4 billion cycles), `wbinvd` (1.6 million cycles), and `nop` (1 cycle). The author uses the technique to break System Management Mode via a related project.
What commenters are saying
Commenters praise the author's previous work, including the Sandsifter opcode bruteforcer and CantorDust visualization tool. Several note the strategic use of subnormals for floating-point slowdowns and MMIO abuse for top scores. A debate emerges over whether using MMIO is 'cheating,' with one commenter arguing that bus cycles can be arbitrarily long on architectures without timeouts. Another camp discusses the throughput-over-latency tradeoff and Wirth's Law, citing Dan Luu's input-lag benchmarks showing an Apple IIe outperforming modern laptops. The thread also highlights the practical application: breaking SMI handlers.